Salim Badakhshan
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MSI MS-95P0 Rev 0a 10 101 Schematic
Technical Specifications
Technical Summary
This Micro-Star motherboard, documented under number AMS-95P0 revision 0A dated 2007/03/20, is built around the Pilot-IPMI platform. The system management and backplane control are handled by an Altera EPM570T100C5N CPLD in a TQFP100 package. This CPLD is programmable via a dedicated JTAG interface, with signals TMS, TCK, TDI, and TDO routed to a programming header (JPLD1), allowing for in-system firmware updates and configuration. The design includes extensive drive bay management, supporting up to 12 hard drives (HDD#0 through HDD#11) with individual activity and fault LED indicators, as well as slot presence detection. The board utilizes a 32.768 KHz real-time clock oscillator (OSC1) and features multiple GPIO and SGPIO interfaces for backplane communication.
Technician FAQ
Q: What is the main programmable controller on this motherboard?
A: The main controller is an Altera EPM570T100C5N CPLD in a TQFP100 package.
Q: Is the CPLD programmable on this motherboard?
A: Yes, the EPM570T100C5N CPLD is programmable via a dedicated JTAG header (JPLD1) with TMS, TCK, TDI, and TDO signals.
Q: What is the platform architecture of this motherboard?
A: This motherboard is based on the Pilot-IPMI platform, designed for server backplane and drive bay management.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
Technical Summary
This MICRO-STAR MS-95P0 Rev 1.0 motherboard, dated August 3, 2007, is based on the Pilot2 project and utilizes the Pilot-IPMI platform. The board is controlled by an Altera EPM570T100C5N CPLD, housed in a TQFP100 package, which serves as the embedded controller and is programmable via JTAG. The design includes a DSD (Drive Status Display) controller for SAS/SATA backplane management, supporting up to 12 hard drives with individual activity and fault LED indicators. The CPLD manages global fault and activity signals, as well as SGPIO interface communication for drive bay status reporting.
Technician FAQ
Q: What is the embedded controller on this MS-95P0 board?
A: The board uses an Altera EPM570T100C5N CPLD (U1) in a TQFP100 package.
Q: Is the CPLD programmable on this motherboard?
A: Yes, the EPM570T100C5N CPLD is programmable via JTAG interface (TMS, TCK, TDI, TDO).
Q: What is the primary function of this board?
A: This is a Pilot-IPMI backplane controller board designed for SAS/SATA drive bay management with DSD (Drive Status Display) support for up to 12 HDDs.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
Technical Summary
This MICRO-STAR motherboard, documented under board number MS-95P0 and revision 1.0, is dated Friday, August 03, 2007. The board utilizes an Altera EPM570T100C5N CPLD as the embedded controller, housed in a TQFP100 package. This CPLD is programmable via a dedicated JTAG interface, with signals TMS, TCK, TDI, and TDO present on the schematic for in-system programming. The design includes a DSD (Drive Status Display) controller for HDD activity and fault indication, supporting up to 12 drives with individual green/fail LEDs and mate notification.
Technician FAQ
Q: What is the EC/KBC on this motherboard?
A: The EC/KBC is an Altera EPM570T100C5N CPLD in a TQFP100 package.
Q: Is the EC/KBC programmable on this motherboard?
A: Yes, the EPM570T100C5N CPLD is programmable via a JTAG interface, with TMS, TCK, TDI, and TDO signals available.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | MICRO-STAR |
| Document Number | AMS-95P0 |
| Revision | 0A |
| Date | 2007/03/20 |
| CPU Platform | Pilot-IPMI |
| EC / KBC | EPM570T100C5N |
| EC/KBC Package | TQFP100 |
| EC/KBC Programmable | Yes (JTAG: TMS, TCK, TDI, TDO) |
Technical Summary
This Micro-Star motherboard, documented under number AMS-95P0 revision 0A dated 2007/03/20, is built around the Pilot-IPMI platform. The system management and backplane control are handled by an Altera EPM570T100C5N CPLD in a TQFP100 package. This CPLD is programmable via a dedicated JTAG interface, with signals TMS, TCK, TDI, and TDO routed to a programming header (JPLD1), allowing for in-system firmware updates and configuration. The design includes extensive drive bay management, supporting up to 12 hard drives (HDD#0 through HDD#11) with individual activity and fault LED indicators, as well as slot presence detection. The board utilizes a 32.768 KHz real-time clock oscillator (OSC1) and features multiple GPIO and SGPIO interfaces for backplane communication.
Technician FAQ
Q: What is the main programmable controller on this motherboard?
A: The main controller is an Altera EPM570T100C5N CPLD in a TQFP100 package.
Q: Is the CPLD programmable on this motherboard?
A: Yes, the EPM570T100C5N CPLD is programmable via a dedicated JTAG header (JPLD1) with TMS, TCK, TDI, and TDO signals.
Q: What is the platform architecture of this motherboard?
A: This motherboard is based on the Pilot-IPMI platform, designed for server backplane and drive bay management.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | MICRO-STAR |
| Document Number | MS-95P0 |
| Revision | 1.0 |
| Date | Friday, August 03, 2007 |
| Board Number | MS-95P0 |
| Project Code | Pilot2 |
| CPU Platform | Pilot-IPMI |
| EC / KBC | epm570t100c5n/"]U1 EPM570T100C5N[/URL] |
| EC/KBC Package | TQFP100 |
| EC/KBC Programmable | Yes (CPLD) |
Technical Summary
This MICRO-STAR MS-95P0 Rev 1.0 motherboard, dated August 3, 2007, is based on the Pilot2 project and utilizes the Pilot-IPMI platform. The board is controlled by an Altera EPM570T100C5N CPLD, housed in a TQFP100 package, which serves as the embedded controller and is programmable via JTAG. The design includes a DSD (Drive Status Display) controller for SAS/SATA backplane management, supporting up to 12 hard drives with individual activity and fault LED indicators. The CPLD manages global fault and activity signals, as well as SGPIO interface communication for drive bay status reporting.
Technician FAQ
Q: What is the embedded controller on this MS-95P0 board?
A: The board uses an Altera EPM570T100C5N CPLD (U1) in a TQFP100 package.
Q: Is the CPLD programmable on this motherboard?
A: Yes, the EPM570T100C5N CPLD is programmable via JTAG interface (TMS, TCK, TDI, TDO).
Q: What is the primary function of this board?
A: This is a Pilot-IPMI backplane controller board designed for SAS/SATA drive bay management with DSD (Drive Status Display) support for up to 12 HDDs.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | MICRO-STAR |
| Document Number | MS-95P01 |
| Revision | 1.0 |
| Date | Friday, August 03, 2007 |
| Board Number | MS-95P0 |
| EC / KBC | epm570t100c5n/"]U1 EPM570T100C5N[/URL] |
| EC/KBC Package | TQFP100 |
| EC/KBC Programmable | Yes (CPLD, JTAG: TMS, TCK, TDI, TDO) |
Technical Summary
This MICRO-STAR motherboard, documented under board number MS-95P0 and revision 1.0, is dated Friday, August 03, 2007. The board utilizes an Altera EPM570T100C5N CPLD as the embedded controller, housed in a TQFP100 package. This CPLD is programmable via a dedicated JTAG interface, with signals TMS, TCK, TDI, and TDO present on the schematic for in-system programming. The design includes a DSD (Drive Status Display) controller for HDD activity and fault indication, supporting up to 12 drives with individual green/fail LEDs and mate notification.
Technician FAQ
Q: What is the EC/KBC on this motherboard?
A: The EC/KBC is an Altera EPM570T100C5N CPLD in a TQFP100 package.
Q: Is the EC/KBC programmable on this motherboard?
A: Yes, the EPM570T100C5N CPLD is programmable via a JTAG interface, with TMS, TCK, TDI, and TDO signals available.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
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