Reputation:
asus g505-c872mpi 1
Technical Specifications
Technical Summary
This ASUS G505-SL-1GD3-DI-DP graphics card, identified by ASUS P/N 60YV02N0-VG0A01 and board code G505 (C872MPI), is built around the NVIDIA GeForce505 GPU with part number 02G190016720DP. It utilizes a PCI Express 2.0 bus standard and is equipped with 1GB of GDDR3 video memory. The documentation was authored by Medison_Huang of the CSC-GRMA department and dated April 16, 2012.
Technician FAQ
Q: What is the GPU model used on this ASUS G505 card?
A: The graphics engine is an NVIDIA GeForce505 GPU with P/N 02G190016720DP.
Q: What is the video memory configuration?
A: The card features 1GB of GDDR3 video memory.
Q: What bus standard does this card use?
A: It uses the PCI Express 2.0 bus standard.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Technical Specifications
| Parameter | Value |
|---|---|
| Brand | ASUS |
| Model | G505-SL-1GD3-DI-DP |
| ASUS P/N | 60YV02N0-VG0A01 |
| Graphics Engine | NVIDIA GeForce505 GPU |
| GPU P/N | 02G190016720DP |
| Bus Standard | PCI Express 2.0 |
| Video Memory | GDDR3 1GB |
| Board Code | G505 (C872MPI) |
| Date | Apr/16/2012 |
| Author | Medison_Huang |
| Department | CSC-GRMA |
Technical Summary
This ASUS G505-SL-1GD3-DI-DP graphics card, identified by ASUS P/N 60YV02N0-VG0A01 and board code G505 (C872MPI), is built around the NVIDIA GeForce505 GPU with part number 02G190016720DP. It utilizes a PCI Express 2.0 bus standard and is equipped with 1GB of GDDR3 video memory. The documentation was authored by Medison_Huang of the CSC-GRMA department and dated April 16, 2012.
Technician FAQ
Q: What is the GPU model used on this ASUS G505 card?
A: The graphics engine is an NVIDIA GeForce505 GPU with P/N 02G190016720DP.
Q: What is the video memory configuration?
A: The card features 1GB of GDDR3 video memory.
Q: What bus standard does this card use?
A: It uses the PCI Express 2.0 bus standard.
Technical data structured and organized by Dr-Bios.com, based on original schematic source analysis.
Attachments
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